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this is information on a product in full production. march 2014 docid023128 rev 5 1/44 A7985A 2 a step-down switching regulato r for automotive applications datasheet - production data features ? 2 a dc output current ? qualified following aec -q100 requirements (see ppap for more details) ? 4.5 v to 38 v input voltage ? output voltage adjustable from 0.6 v ? 250 khz switching frequency, programmable up to 1 mhz ? internal soft-start and enable ? low dropout op eration: 100% duty cycle ? voltage feed-forward ? zero load current operation ? overcurrent and thermal protection ? hsop8 package applications ? dedicated to automotive applications ? automotive led driving description the A7985A is a step-down switching regulator with a 2.5 a (minimum) current limited embedded power mosfet, so it is able to deliver up to 2 a current to the load depending on the application conditions. the input voltage can range from 4.5 v to 38 v, while the output voltage can be set starting from 0.6 v to v in . requiring a minimum set of external components, the device includes an internal 250 khz switching frequency oscillator that can be externally adjusted up to 1 mhz. the hsop8 package with exposed pad allows the reduction of r th(ja) down to 40 c/w. figure 1. application circuit hsop8 exposed pad 287 )% 6<1&+ (1 *1' &203 9&& 9,1 9wr9 $$ &lq &rxw & 5 5 ' / 9rxw 9wr 9&& 5 )6: & $0y www.st.com
contents A7985A 2/44 docid023128 rev 5 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.1 type iii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.2 type ii compensation networ k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
docid023128 rev 5 3/44 A7985A contents 44 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables A7985A 4/44 docid023128 rev 5 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. input mlcc capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. hsop8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
docid023128 rev 5 5/44 A7985A list of figures 44 list of figures figure 1. application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. sawtooth: voltage and frequen cy feed-forward; external synchroni zation . . . . . . . . . . . . . 12 figure 6. oscillator frequency vs . the fsw pin resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. soft-start scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. the error amplifier, the pwm modulator and the lc output filter . . . . . . . . . . . . . . . . . . . . 21 figure 10. type iii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. open loop gain: module bode diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. open loop gain bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. type ii compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. open loop gain: module bode diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. open loop gain bode diagram with electrolytic /tantalum output capacitor . . . . . . . . . . . . . 28 figure 16. switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. pcb layout: A7985A (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. pcb layout: A7985A (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. pcb layout: A7985A (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 22. junction temperature vs. output current at v in = 24 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 23. junction temperature vs. output current at v in = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 24. junction temperature vs. output current at v in = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25. efficiency vs. output current at v o = 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26. efficiency vs. output current at v o = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 27. efficiency vs. output current at v o = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 28. load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 29. line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 30. load transient: from 0.4 a to 2 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 31. soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 32. short-circuit behavior at v in = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 33. short-circuit behavior at v in = 24 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 34. positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 35. maximum output current accordin g to max. dc switch current (2.0 a): v o = 12 v. . . . . . . 38 figure 36. inverting buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 37. maximum output current according to switch max. peak current (2.0 a): v o = -5 v. . . . . . 39 figure 38. hsop8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
pin settings A7985A 6/44 docid023128 rev 5 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description table 1. pin description n. type description 1 out regulator output. 2 synch master/slave synchronization. when it is left floating, a signal with a phase shift of half a period in respect to the power turn-on is present at the pin. when connected to an external signal at a frequency higher than the internal one, the device is synchronized by the external signal, with zero phase shift. connecting together the synch pins of two devices, the one with the higher frequency works as master and the other as slave; so the two power turn-ons have a phase shift of half a period. 3en a logical signal (active high) enables the device. with en higher than 1.2 v the device is on and with en lower than 0.63 v the device is off. 4 comp error amplifier output to be used for loop frequency compensation. 5fb feedback input. connecting the output voltage directly to this pin the output voltage is regulated at 0.6 v. to have higher regulated voltages an external resistor divider is required from v out to the fb pin. 6fsw the switching frequency can be increased connecting an external resistor from the fsw pin and ground. if this pin is left floating the device works at its free-running frequency of 250 khz. 7 gnd ground. 8v cc unregulated dc input voltage.
docid023128 rev 5 7/44 A7985A maximum ratings 44 2 maximum ratings 3 thermal data table 2. absolute maximum ratings symbol parameter value unit v cc input voltage 45 v out output dc voltage -0.3 to v cc f sw , comp, synch analog pin -0.3 to 4 en enable pin -0.3 to v cc fb feedback voltage -0.3 to 1.5 p tot power dissipation at t a < 60 c hsop8 2 w t j junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r th(ja) maximum thermal resistance junction ambient (1) hsop8 40 c/w 1. package mounted on demonstration board.
electrical characteristics A7985A 8/44 docid023128 rev 5 4 electrical characteristics t j = -40 c to 125 c, v cc = 12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test conditions values unit min. typ. max. v cc operating input voltage range 4.5 38 v v ccon turn-on v cc threshold 4.5 v cchys v cc uvlo hysteresis 0.1 0.4 r ds(on) mosfet on-resistance 200 400 m ? i lim maximum limiting current 2.5 3.5 a oscillator f sw switching frequency 210 250 275 khz v fsw fsw pin voltage 1.254 v d duty cycle 0 100 % f adj adjustable switching frequency r fsw = 33 k ? 1000 khz dynamic characteristics v fb feedback voltage 4.5 v < v cc < 38 v 0.588 0.6 0.612 v dc characteristics i q quiescent current duty cycle = 0, v fb = 0.8 v 2.4 ma i qst-by total standby quiescent current 20 30 ? a enable v en en threshold voltage device off level 0.3 v device on level 1.2 i en en current en = v cc 7.5 10 a soft-start t ss soft-start duration fsw pin floating 7.3 8.2 9.8 ms f sw = 1 mhz, r fsw = 33 k ? 2 error amplifier v ch high level output voltage v fb < 0.6 v 3 v v cl low level output voltage v fb > 0.6 v 0.1 i o source source comp pin v fb = 0.5 v, v comp = 1 v 19 ma i o sink sink comp pin v fb = 0.7 v, v comp = 0.75 v 30 ma g v open loop voltage gain (1) 100 db
docid023128 rev 5 9/44 A7985A electrical characteristics 44 synchronization function v s_in,hi high input voltage 2 3.3 v v s_in,lo low input voltage 1 t s_in_pw input pulse width v s_in,hi = 3 v, v s_in,lo = 0 v 100 ns v s_in,hi = 2 v, v s_in,lo = 1 v 300 i synch,lo slave sink current v synch = 2.9 v 0.7 1 ma v s_out,hi master output amplitude i source = 4.5 ma 2 v t s_out_pw output pulse width synch floating 110 ns protection t shdn thermal shutdown 150 c hysteresis 30 1. guaranteed by design. table 4. electrical ch aracteristics (continued) symbol parameter test conditions values unit min. typ. max.
functional description A7985A 10/44 docid023128 rev 5 5 functional description the A7985A device is based on a ?voltage mo de?, constant frequency control. the output voltage v out is sensed by the feedback pin (fb) co mpared to an internal reference (0.6 v) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch. the main internal blocks are shown in the block diagram in figure 3 . they are: ? a fully integrated osc illator that provides sawtooth to modulate the duty cycle and the synchronization signal. its switching frequency can be adjusted by an external resistor. the voltage and frequency feed-forward are implemented ? soft-start circuitry to limit inrush current during the startup phase ? voltage mode error amplifier ? pulse width modulator and the relative logic circuitry necessary to drive the internal power switch ? high-side driver for embedded p-channel power mosfet switch ? peak current limit sensing block, to ha ndle overload and short-circuit conditions ? a voltage regulator and internal reference. it supplies internal circuitry and provides a fixed internal reference ? a voltage monitor circuitry (uvlo) that checks the input and internal voltages ? a thermal shutdown block, to prevent th ermal runaway. figure 3. block diagram peak current limit oscillator s r q thermal shutdown soft- start en trimming uvlo 0.6v regulator & bandgap 1.254v 3.3v synch & phase shift en fb comp fsw gnd synch out vcc driver e/a pwm peak current limit oscillator s r q thermal shutdown soft- start en trimming uvlo uvlo 0.6v regulator & bandgap regulator & bandgap 1.254v 3.3v synch & phase shift en fb comp fsw gnd synch out vcc driver e/a pwm
docid023128 rev 5 11/44 A7985A functional description 44 5.1 oscillator and synchronization figure 4 shows the block diag ram of the oscillator circuit. t he internal osc illator provides a constant frequency clock. its frequency depe nds on the resistor externally connected to the fsw pin. if the fsw pin is left floating, the frequency is 250 khz; it can be increased as shown in figure 6 by an external resistor connected to ground. to improve the line transient performance, ke eping the pwm gain const ant versus the input voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth according to the input voltage change (see figure 5 .a). the slope of the sawtooth also changes if the oscillator fr equency is incr eased by the external resistor. in this way, a fr equency feed-forward is implemented ( figure 5 .b) in order to keep the pwm gain constant versus the switching frequency (see section 6.4 on page 20 for pwm gain expression). on the synch pin the synchronization signal is generated. this signal has a phase shift of 180 with respect to the clock. this delay is useful when two devices are synchronized connecting the synch pin together. when synch pins are connected, the device with the higher oscillator frequency works as master, so the slave device switc hes at the frequency of the master but with a delay of half a pe riod. this minimizes the rms current flowing through the input capacitor (see the l5988d datasheet). figure 4. oscillator circuit block diagram the device can be synchronized to work at a higher frequency feeding an external clock signal. the synchronization changes the sawtooth amplitude, changing the pwm gain ( figure 5 .c). this change must be taken into ac count when the loop stability is studied. to minimize the change of the pwm gain, the free-running frequency should be set (with a resistor on the fsw pin) only slightly lower than the external clock frequency. this pre- adjusting of the frequency changes the sawtooth slope in order to render negligible the truncation of sawtooth, due to the external synchronization. clock generator ramp generator fsw sawtooth clock synchronization synch clock generator ramp generator fsw sawtooth clock clock synchronization synch
functional description A7985A 12/44 docid023128 rev 5 figure 5. sawtooth: voltage and frequency feed-forward; external synchronization figure 6. oscillator frequency vs. the fsw pin resistor 5 )6: >n2kpv@ ) 6: >n+]@
docid023128 rev 5 13/44 A7985A functional description 44 where: equation 1 f sw is desired switching frequency. 5.2 soft-start soft-start is essential to assure the correct and safe startup of the step-down converter. it avoids inrush current surge and makes the output voltage increase monothonically. the soft-start is performed by a staircase ramp on the non inverting input (v ref ) of the error amplifier. so the output voltage slew rate is: equation 2 where sr vref is the slew rate of the non inverting input, while r1 and r2 is the resistor divider to regulate the output voltage (see figure 7 ). the soft-start staircase consists of 64 steps of 9.5 mv each, from 0 v to 0.6 v. the ti me base of one step is of 32 clock cycles. so the soft-start time and then the output voltag e slew rate depend on the switching frequency. figure 7. soft-start scheme soft-start time results: equation 3 for example, with a switching frequency of 250 khz, the ss time is 8 ms. r fsw 28.5 10 9 ? f sw 250 10 3 ? ? ----------------------------------------- 3.23 10 3 ? ? = sr out sr vref 1 r1 r2 ------- - + ?? ?? ? = ss time 32 64 ? fsw ----------------- =
functional description A7985A 14/44 docid023128 rev 5 5.3 error amplifier and compensation the error amplifier (e/a) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. its non invert ing input is internally connected to a 0.6 v voltage reference, while its inverting input (fb) and output (comp) are externally available for feedback and frequency compensation. in this device the error amplifier is a voltage mode operational amplifier, so with high dc gain and low output impedance. the uncompensated error amplifie r characteristics are shown in table 5 . in continuous conduction mode (ccm), the tran sfer function of the power section has two poles due to the lc filter and one zero due to the esr of the output capacitor. different kinds of compensation networks can be used depending on the esr value of the output capacitor. in case the zero introduced by the output capaci tor helps to compensate the double pole of the lc filter, a type ii compen sation network can be used. otherwise, a type iii compensation network must be used (see section 6.4 on page 20 for details of the compensation network selection). the methodology to compensate the loop is to introduce zeroes to obtain a safe phase margin. 5.4 overcurrent protection the A7985A implements the overcurrent prot ection sensing current flowing through the power mosfet. due to the noise created by th e switching activity of the power mosfet, the current sensing is disabled during the init ial phase of the conduc tion time. this avoids an erroneous detection of a fault condition. this interval is generally known as ?masking time? or ?blanking time?. the masking time is about 200 ns. if the overcurrent limit is reached, the power mosfet is turned off, implementing the pulse- by-pulse overcurrent protection. under an over current condition, the device can skip turn-on pulses in order to keep the output current cons tant and equal to the current limit. if, at the end of the ?masking time?, the current is high er than the overcurrent threshold, the power mosfet is turned off and one pulse is skipped . if, at the following s witching-on, when the ?masking time? ends, the current is still higher than the overcurrent threshold, the device skips two pulses. this mechanism is repeated and the device can skip up to seven pulses. while, if at the end of the ?maski ng time? the current is lower than the over current threshold, the number of skipped cycles is decreased by one unit (see figure 8 ). so the overcurrent/short-circuit protection acts by switching off the power mosfet and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit. table 5. uncompensated error amplifier characteristics parameter value low frequency gain 100 db gbwp 4.5 mhz slew rate 7 v/ ? s output voltage swing 0 to 3.3 v maximum source/sink current 17 ma/25 ma
docid023128 rev 5 15/44 A7985A functional description 44 this kind of overcurrent protection is effective if the output current is limited. to prevent the current from diverging, the current ripple in the inductor during the on-time must not be higher than the current ripple during the off-time. that is: equation 4 if the output voltage is shorted, v out ?? 0, i out = i lim , d/f sw = t on_min , (1-d)/f sw ?? 1/f sw . so from the above equation the maximum switch ing frequency that guarantees to limit the current results: equation 5 with r ds(on) = 300 m ? , drc = 0.08 ? , the worst condition is with v in = 38 v, i lim = 2.5 a; the maximum frequency to keep the output current limited during the short-circuit results 74 khz. based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one eighth, the maximum f sw , adjusted by the fsw pin, that assures a full effective output current limitation is 74 khz * 8 = 592 khz. if, with v in = 38 v, the switching frequency is set hi gher than 592 khz, during short-circuit condition the syst em finds a different equ ilibrium with higher curren t. for example, with f sw = 700 khz and the output shorted to ground, the output current is limited around: equation 6 where f sw * is 700 khz divided by eight. v in v ? out r dson i out ? dcr i out ? ? ? lf sw ? ------------------------------------------------------------------------------------------------------------ d ? v out v f r dson i out ? dcr i out ? ++ + lf sw ? ----------------------------------------------------------------------------------------------------------- 1d ? ?? ? = f sw * v f dcr i ? + lim ?? v in r dson dcr + ?? i lim ? ? ?? ------------------------------------------------------------------------------ - 1 t on_min ---------------------- ? = i out v in f sw * ? v f t on_min ? ? drc t on_min ? ?? r dson dcr + ?? f sw * ? + --------------------------------------------------------------------------------------------------------------- - 3.68a ==
functional description A7985A 16/44 docid023128 rev 5 figure 8. overcurrent protection 5.5 enable function the enable feature allows the device to be put into standby mode. with the en pin lower than 0.3 v, the device is disabled and th e power consumption is reduced to less than 30 ?? a. with the en pin lower than 1.2 v, the device is enabled. if the en pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v cc compatible. 5.6 hysteretic thermal shutdown the thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 c. once the junction temperature goes back to about 120 c, the device restarts in normal operation. the sensing element is very close to the pdmos area, so ensuring an accurate and fast temperature detection.
docid023128 rev 5 17/44 A7985A application information 44 6 application information 6.1 input capacitor selection the capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum rms input current required by the device. the input capacitor is subject to a pulsed current, the rm s value of which is dissipated over its esr, affecting the overa ll system efficiency. so the input capacitor must have an rms current rating higher than the maximum rms input current and an esr value compliant with the expected efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 7 where i o is the maximum dc output current, d is the duty cycle, ? ? is the efficiency. considering ?? = 1, this function has a maximum at d = 0.5 and it is equal to io/2. in a specific application the ra nge of possible duty cycles must be considered in order to find out the maximum rms input current. the maximum and minimum duty cycles can be calculated as: equation 8 and equation 9 where v f is the forward voltage on the freewheeling diode and v sw is voltage drop across the internal pdmos. the peak-to-peak voltage across the input capacitor can be calculated as: equation 10 where esr is the equivalent series resistance of the capacitor. given the physical dimension, ceramic capaci tors can well meet the requirements of the input filter sustaining a higher input rms current than electrolytic/tantalum types. i rms i o d 2d 2 ? ? -------------- - ? d 2 ? 2 ------ - + ? = d max v out v f + v inmin v sw ? ------------------------------------ - = d min v out v f + v inmax v sw ? -------------------------------------- = v pp i o c in f sw ? ------------------------- 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? esr i o ? + ? =
application information A7985A 18/44 docid023128 rev 5 in this case, the equation of c in as a function of the target v pp can be written as follows: equation 11 neglecting the small esr of ceramic capacitors. considering ?? = 1, this function has its maximum in d = 0.5, therefore, given the maximum peak-to-peak input voltage (v pp_max ), the minimum input capacitor (c in_min ) value is: equation 12 typically, c in is dimensioned to keep the maximum peak-to-peak voltage in the order of 1% of v inmax . in table 6 , some multi-layer ceramic capacitors su itable for this device are reported. a ceramic bypass capacitor, as close to the vcc and gnd pins as possible, so that additional parasitic esr and esl are minimized, is suggested in orde r to prevent instability on the output voltage due to noise. the value of the bypass capacitor can go from 100 nf to 1 f. 6.2 inductor selection the inductance value fixes the current ripple flowing through the output capacitor. so the minimum inductance value in order to have the expected current ripple must be selected. the rule to fix the current ripple value is to have a ripple at 20% -40% of the output current. in continuous current mode (ccm), the induct ance value can be calculated by the following equation: equation 13 where t on is the conduction time of th e internal high-side switch and t off is the conduction time of the external diode (in ccm, f sw = 1/(t on + t off )). the maximum current ripple, at fixed v out , is obtained at maximum t off , that is at minimum duty cycle (see section 6.1 to calculate minimum duty). so by fixing ? i l = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: table 6. input mlcc capacitors manufacturer series cap value ( ? f) rated voltage (v) taiyo yuden umk325bj106mm-t 10 50 gmk325bj106mn-t 10 35 murata grm32er71h475k 4.7 50 c in i o v pp f sw ? -------------------------- - 1 d ? --- - ? ?? ?? d d ? --- - 1d ? ?? ? + ? ? = c in_min i o 2v pp_max f sw ?? ----------------------------------------------- - = ? i l v in v out ? l ----------------------------- - t on ? v out v f + l --------------------------- - t off ? ==
docid023128 rev 5 19/44 A7985A application information 44 equation 14 where f sw is the switching frequency, 1/(t on + t off ). for example, for v out = 5 v, v in = 24 v, i o = 2 a and f sw = 250 khz, the minimum inductance value to have ? i l = 30% of i o is about 28 ? h. the peak current through the inductor is given by: equation 15 so if the inductor value decreases, then the peak current (that must be lower than the minimum current limit of the device) increases. according to the maximum dc output current for this product family (2 a), the higher the inductor value, the higher the average output current that can be delivered, wit hout triggering the overcurrent protection. in table 7 some inductor part numbers are listed. 6.3 output capacitor selection the current in the capacitor has a triangular waveform which generates a voltage ripple across it. this ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its esr). so the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. the amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. equation 16 usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (mlcc) with very low esr value. table 7. inductors manufacturer series inductor value ( ? h) saturation current (a) coilcraft mss1038 3.8 to 10 3.9 to 6.5 mss1048 12 to 22 3.84 to 5.34 wurth pd type l 8.2 to 15 3.75 to 6.25 pd type m 2.2 to 4.7 4 to 6 sumida cdrh6d226/hp 1.5 to 3.3 3.6 to 5.2 cdr10d48mn 6.6 to 12 4.1 to 5.7 l min v out v f + ? i max --------------------------- - 1d min ? f sw ---------------------- - ? = i lpk ? i o ? i l 2 -------- + = ? v out esr ? i max ? ? i max 8c out f sw ?? ------------------------------------ - + =
application information A7985A 20/44 docid023128 rev 5 the output capacitor is important also for loop st ability: it fixes the double lc filter pole and the zero due to its esr. in section 6.4 , how to consider its effect in the system stability is illustrated. for example, with v out = 5 v, v in = 24 v, ? i l = 0.9 a (resulting by the inductor value), in order to have a ? v out = 0.01 v out , if the multi-layer cerami c capacitors are adopted, 10 f are needed and the esr effect on the output voltage ripple can be neglected. in case of not-negligible esr (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its esr value. so, in the case of 330 f with esr = 70 m ??? the resistive component of the drop dominates and the voltage ripple is 43 mv ? the output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. when the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. so if the high slew rate load transient is required by the applicat ion, the output capacitor and system bandwidth must be chosen in order to sustain the load transient. in table 8 below some capacitor series are listed. 6.4 compensation network the compensation network must assure stabilit y and good dynamic pe rformance. the loop of the A7985A is based on the voltage mode control. the error amplifier is a voltage operational amplifier with high ban dwidth. so by selecting the compensation network the e/a is considered as ideal, that is, its bandwidth is much larger than the system one. the transfer functions of the pwm modulator and the output lc filter are studied (see figure 10 ). the transfer function of the pwm modulator, from the error amplifier output (comp pin) to the out pin, results: equation 17 where v s is the sawtooth amplitude. as seen in section 5.1 on page 11 , the voltage feed- forward generates a sawtooth amplitude directly proportional to the input voltage, that is: equation 18 table 8. output capacitors manufacturer series cap value ( ? f) rated voltage (v) esr (m ? ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 g pw0 v in v s -------- - = v s kv in ? =
docid023128 rev 5 21/44 A7985A application information 44 in this way the pwm modulator gain results constant and equal to: equation 19 the synchronization of the device with an external cl ock provided through the synch pin can modify the pwm modulator gain (see section 5.1 on page 11 to understand how this gain changes and how to keep it constant in spite of the external synchronization). figure 9. the error amplifier, the pwm modulator and the lc output filter the transfer function on the lc filter is given by: equation 20 where: equation 21 equation 22 as seen in section 5.3 on page 14 , two different kinds of network can compensate the loop. in the two following paragraphs the guidelines to select the type ii and type iii compensation network are illustrated. g pw0 v in v s -------- - 1 k --- - 18 === fb comp v ref e/a pwm v s out v cc c out esr l g pw0 g lc fb comp v ref e/a pwm v s out v cc c out esr l g pw0 g lc g lc s ?? 1 s 2 ? f zesr ? ------------------------- - + 1 s 2 ? qf ? lc ? ---------------------------- s 2 ? f lc ? ------------------- ?? ?? 2 ++ ------------------------------------------------------------------------- = f lc 1 2 ? lc out ? 1 esr r out -------------- - + ?? ----------------------------------------------------------------------- - = f zesr 1 2 ? esr c out ?? ------------------------------------------- - = ? + ?? ?? ? lc out r out esr ?? + ------------------------------------------------------------------------------------------ r out v out i out -------------- = , =
application information A7985A 22/44 docid023128 rev 5 6.4.1 type iii compensation network the methodology to stabilize t he loop consists in placing tw o zeroes to co mpensate the effect of the lc double pole, thereby increasin g phase margin; then to place one pole in the origin to minimize the dc error on the regulated output voltage; finally to place other poles far from the zero db frequency. if the equivalent series resistance (esr) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 ???? esr ?? c out < 1 / bw), the type iii compensation network is needed. multi-laye r ceramic capacitors (mlcc) have very low esr (< 1 m ? ), with very high frequency zero, so a type iii network is adopted to compensate the loop. in figure 10 , the type iii compensation network is shown. this network introduces two zeroes (f z1 , f z2 ) and three poles (f p0 , f p1 , f p2 ). they are expressed as: equation 23 equation 24 figure 10. type iii compensation network f z1 1 2 ? c 3 r 1 r 3 + ?? ?? ------------------------------------------------ = f z2 1 2 ? r 4 c 4 ?? ----------------------------- - = ? f p0 0 = f p1 1 2 ? r 3 c 3 ?? ----------------------------- - = f p2 1 2 ? r 4 c 4 c 5 ? c 4 c 5 + -------------------- ?? ------------------------------------------- - = ??
docid023128 rev 5 23/44 A7985A application information 44 in figure 11 the bode diagram of the pwm and lc filter transfer function (g pw0 g lc (f)) and the open loop gain (g loop (f) = g pw0 g lc (f) g typeiii (f)) are drawn. figure 11. open loop gain: module bode diagram the guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows: 1. choose a value for r 1 , usually between 1 k ? and 5 k ? . 2. choose a gain (r 4 /r 1 ) in order to have the required bandwidth (bw), that means: equation 25 where k is the feed-forward constant and 1/k is equal to 18. 3. calculate c 4 by placing the zero at 50% of the output filter double pole frequency (f lc ): equation 26 4. calculate c 5 by placing the second pole at fo ur times the system bandwidth (bw): equation 27 5. set also the first pole at four times th e system bandwidth and also the second zero at the output filter double pole: equation 28 r 4 bw f lc --------- - kr 1 ?? = c 4 1 ? r 4 f lc ?? --------------------------- = c 5 c 4 2 ? r 4 c 4 4bw ? 1 ? ??? ------------------------------------------------------------- - = r 3 r 1 4bw ? f lc ----------------- 1 ? -------------------------- - = c 3 1 2 ? r 3 4bw ??? ---------------------------------------- - = ?
application information A7985A 24/44 docid023128 rev 5 the suggested maximum system bandwidth is e qual to the switching frequency divided by 3.5 (f sw /3.5), so lower than 100 khz if the f sw is set higher than 500 khz. for example, with v out = 5 v, v in = 24 v, i o = 2 a, l = 22 ? h, c out = 22 ? f, and esr < 1 m ? , the type iii compensation network is: equation 29 in figure 12 the module and phase of the open loop gain is shown. the bandwidth is about 32 khz and the phase margin is 51 . figure 12. open loop gain bode diagram with ceramic output capacitor r 1 4.99k ? = r 2 680 ? = r 3 270 ? = r 4 1.1k ? = c 3 4.7nf = c 4 47nf = c 5 1pf = ???? ??
docid023128 rev 5 25/44 A7985A application information 44 6.4.2 type ii co mpensation network if the equivalent series resistance (esr) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2 ???? esr ?? c out > 1 / bw), this zero helps stabilize the loop. electrolytic capa citors show not-negl igible esr (> 30 m ? ), so with this kind of output capacitor the type ii networ k combined with the zero of the esr allows the stabilizing of the loop. in figure 13 the type ii network is shown. figure 13. type ii compensation network the singularities of the network are: equation 30 f z1 1 2 ? r 4 c 4 ?? ----------------------------- - = f p0 0 = f p1 1 2 ? r 4 c 4 c 5 ? c 4 c 5 + -------------------- ?? ------------------------------------------- - = ??
application information A7985A 26/44 docid023128 rev 5 in figure 14 the bode diagram of the pwm and lc filter transfer function (g pw0 g lc (f)) and the open loop gain (g loop (f) = g pw0 g lc (f) g typeii (f)) are drawn. figure 14. open loop gain: module bode diagram the guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follows: 1. choose a value for r 1 , usually between 1 k ? and 5 k ? , in order to have values of c4 and c5 not comparable with parasitic capacitance of the board. 2. choose a gain (r 4 /r 1 ) in order to have the required bandwidth (bw), that means: equation 31 where f esr is the esr zero: equation 32 and v s is the sawtooth amplitude. the voltage feed-forward keeps the ratio v s /v in constant. 3. calculate c 4 by placing the zero one decade below the output filter double pole: equation 33 r 4 f esr f lc ----------- - ?? ?? 2 bw f esr ----------- - v s v in -------- - r 1 ??? = f esr 1 2 ? esr c out ?? ------------------------------------------- - = c 4 10 2 ? r 4 f lc ?? ------------------------------ - =
docid023128 rev 5 27/44 A7985A application information 44 4. then calculate c 3 in order to place the second pole at four times the system bandwidth (bw): equation 34 for example, with v out = 5 v, v in = 24 v, i o = 2 a, l = 22 ? h, c out = 330 ? f, and esr = 70 m ?? the type ii compensation network is: equation 35 c 5 c 4 2 ? r 4 c 4 4bw ? 1 ? ??? ------------------------------------------------------------- - = r 1 1.1k ? = r 2 150 ? = r 4 4.99k ? = c 4 180nf = c 5 180pf = ?? ? ?
application information A7985A 28/44 docid023128 rev 5 in figure 15 the module and phase of the open loop gain is shown. the bandwidth is about 36 khz and the phase margin is 53 . figure 15. open loop gain bode diagram with electrolytic/tantalum output capacitor
docid023128 rev 5 29/44 A7985A application information 44 6.5 thermal considerations the thermal design is important to prevent the th ermal shutdown of the device if the junction temperature goes above 150 c. the three differ ent sources of losses within the device are: a) conduction losses due to the not-negligible r ds(on) of the power switch; these are equal to: equation 36 where d is the duty cycle of the application and the maximum r ds(on) overtemperature is 220 m ? . note that the duty cycle is theore tically given by the ratio between v out and v in , but actually it is quite higher to compensate the losses of the regulator. so the conduction losses increase compared with the ideal case. b) switching losses due to power mosf et turn-on and turn-off; these can be calculated as: equation 37 where t rise and t fall are the overlap times of the voltage across the power switch (v ds ) and the current flowing into it during turn-on and turn-off phases, as shown in figure 16 . t sw is the equivalent switching time. for this device the typical value for the equivalent switching time is 40 ns. c) quiescent current lo sses, calculated as: equation 38 where i q is the quiescent current (i q = 2.4 ma). the junction temperature t j can be calculated as: equation 39 where t a is the ambient temperature and p tot is the sum of the power losses just seen. r th(ja) is the equivalent thermal resistance junc tion to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. for this device the path through the exposed pa d is the one conducting the largest amount of heat. the r th(ja) measured on the demonstration board described in the following paragraph is about 40 c/w for the hsop8 package. p on r ds on ?? i out ?? 2 d ?? = p sw v in i out t rise t fall + ?? 2 ------------------------------------------ - fsw ?? ? v in i out t sw f sw ??? == p q v in i q ? = t j t a rth ja p tot ? + =
application information A7985A 30/44 docid023128 rev 5 figure 16. switching losses 6.6 layout considerations the pc board layout of the switching dc/dc r egulator is very import ant to minimize the noise injected in high impedance nodes and interference generated by the high switching current loops. in a step-down converter, the input loop (including the input capacitor, the power mosfet and the freewheeling diode) is the most critical one. this is due to the fact that the high value pulsed current is flowing through it. in or der to minimize the emi, this loop must be as short as possible. the feedback pin (fb) connection to the external resistor divider is a high impedance node, so the interference can be minimized by placin g the routing of the feedback node as far as possible from the high current paths. to reduc e the pick-up noise, the resistor divider must be placed very close to the device. to filter the high frequency noise, a small bypa ss capacitor (220 nf -1 f) can be added as close as possible to the input voltage pin of the device. thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large gr ound plane enhances the thermal performance of the converter allowing high power conversion.
docid023128 rev 5 31/44 A7985A application information 44 in figure 17 a layout example is shown. figure 17. layout example
application information A7985A 32/44 docid023128 rev 5 6.7 application circuit in figure 18 the demonstration board app lication circuit is shown. figure 18. demonstration board application circuit table 9. component list reference part number description manufacturer c1 umk325bj106mm-t 10 ? f, 50 v taiyo yuden c2 grm32er61e226ke15 22 ? f, 25 v murata c3 3.3 nf, 50 v c4 33 nf, 50 v c5 100 pf, 50 v c6 470 nf, 50 v r1 4.99 k ? , 1%, 0.1 w 0603 r2 1.1 k ? , 1%, 0.1 w 0603 r3 330 ? , 1%, 0.1 w 0603 r4 1.5 k ? , 1%, 0.1 w 0603 r5 150 k ??? 1%, 0.1 w 0603 d1 stps3l40 3 a dc, 40 v stmicroelectronics l1 mss1038-103nl 10 ? h, 30%, 3.9 a, dcr max = 35 m ? coilcraft
docid023128 rev 5 33/44 A7985A application information 44 figure 19. pcb layout: A7985A (component side) figure 20. pcb layout: A7985A (bottom side) figure 21. pcb layout: A7985A (front side)
application information A7985A 34/44 docid023128 rev 5 figure 22. junction temperature vs. output current at v in = 24 v figure 23. junction temperature vs. output current at v in = 12 v v out =1.8v v out =3.3v v out =5v hsop vqfn v in =24v f sw =250khz t amb =25 c v out =1.8v v out =3.3v v out =5v hsop vqfn v in =12v f sw =250khz t amb =25 c figure 24. junction temperature vs. output current at v in = 5 v figure 25. efficiency vs. output current at v o = 1.8 v v out =1.2v v out =1.8v v out =3.3v hsop vqfn v in =5v f sw =250khz t amb =25 c 40 45 50 55 60 65 70 75 80 85 0.100 0.600 1.100 1.600 2.100 eff [%] io [a] vin=5v vin=12v vin=24v vo=1.8v fsw=250khz figure 26. efficiency vs. output current at v o =5v figure 27. efficiency vs. output current at v o = 3.3 v 60 65 70 75 80 85 90 95 0.100 0.600 1.100 1.600 2.100 eff [%] io [a] vin=12v vin=18v vin=24v vo=5.0v fsw=250khz 50 55 60 65 70 75 80 85 90 95 0.100 0.600 1.100 1.600 2.100 eff [%] io [a] vin=5v vin=12v vin=24v vo=3.3v fsw=250khz
docid023128 rev 5 35/44 A7985A application information 44 figure 28. load regulation figure 29. line regulation 3.310 3.315 3.320 3.325 3.330 3.335 3.340 3.345 0.00 0.50 1.00 1.50 2.00 v out [v] io [a] vin=5v vin=12v vin=24v 3.3200 3.3250 3.3300 3.3350 3.3400 3.3450 3.3500 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 v out [v] v in [v] io =1a io =2a figure 30. load transient: from 0.4 a to 2 a figure 31. soft-start v out 100mv/div ac coupled i l 500ma/div time base 100us/div v in =24v v out =3.3v c out =47uf l=10uh f sw =520k v out 100mv/div ac coupled i l 500ma/div time base 100us/div v in =24v v out =3.3v c out =47uf l=10uh f sw =520k v out 500mv/div v fb 200mv/div i l 500ma/div time base 1ms/div figure 32. short-circuit behavior at v in = 12 v figure 33. short-circuit behavior at v in = 24 v out 5v/div i l 1a/div v out 1v/div synch 5v/div timebase 10us/div out 5v/div i l 0.5a/div v out 1v/div synch 5v/div timebase 10us/div
application ideas A7985A 36/44 docid023128 rev 5 7 application ideas 7.1 positive buck-boost the A7985A can implement the step-up/down converter with a positive output voltage. figure 34 shows the schematic: one power mosfet and one schottky diode are added to the standard buck topology to provide a 12 v outp ut voltage with input voltage from 4.5 v to 38 v. figure 34. positive buck-boost regulator the relationship between input and output voltage is: equation 40 so the duty cycle is: equation 41 the output voltage isn?t limited by the maximum operating voltage of the device (38 v), because the output voltage is sensed only thro ugh the resistor divider. the external power mosfet maximum drain to source voltage, must be higher than output voltage; the maximum gate to source voltage must be higher than the input voltage (in figure 34 , if v in is higher than 16 v, the gate must be protected through a zener diode and resistor). 9&& *1' )6: )% 287 6<1& (1 &203 73 $$ 9,1 9287 & ?) & q) 5 & s) 5 5 / ?+ ' 6736/8 & ?) ' 6736/8 0 6711)/ 5 5 & q) & ?) *1' *1' 5 $0 v out v in d 1d ? ------------- ? = d v out v out v in + ----------------------------- - =
docid023128 rev 5 37/44 A7985A application ideas 44 the current flowing thro ugh the internal power mosfet is transferred to the load only during the off time, so according to the maxi mum dc switch current (2.0 a), the maximum output current for the buck boost topology can be calculated from equation 42 . equation 42 where i sw is the average current in the embedded power mosfet in the on time. to chose the right value of the inductor and to manage transient output current, which, for a short time, can exceed the maximum output current calculated by equation 42 , also the peak current in the power mosfet must be calculated. the peak current, shown in equation 43 , must be lower than the mini mum current limit (2.5 a). equation 43 where r is defined as the ratio between the inductor current ripple and the inductor dc current. therefore, in the buck boost topology t he maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value). in figure 35 the maximum output current for the above configuration is depicted, varying the input voltage from 4.5 v to 38 v. the dashed line considers a more accurate estimation of the duty cycles given equation 44 , where power losses across diodes, the exte rnal power mosfet, an d the internal power mosfet are taken into account. i sw i out 1d ? ------------- 2 a ? = i sw,pk i out 1d ? ------------- 1 r 2 -- - + 3.7a ? ? = r v out i out lf sw ?? ------------------------------------ 1d ? ?? 2 ? =
application ideas A7985A 38/44 docid023128 rev 5 figure 35. maximum ou tput current according to max. dc switch current (2.0 a): v o = 12 v equation 44 where v d is the voltage drop across the diodes, v sw and v swe across the internal and external power mosfet. 7.2 inverting buck-boost the A7985A device can implement the step -up/down converter with a negative output voltage. figure 34 shows the schematic to regulate -5 v: no further external components are added to the standard buck topology. the relationship between input and output voltage is: equation 45 so the duty cycle is: equation 46 as in the positive one, in the inverting buck-boost the current flowing through the power mosfet is transferred to the load only durin g the off time. so acco rding to the maximum dc switch current (2.0 a), the maximum output current can be calculated from equation 42 , where the duty cycle is given by equation 46 . d v out 2v d ? + v in v sw v swe v out 2v ? d ++ ? ? ------------------------------------------------------------------------------------------- - = v out v in ? d 1d ? ------------- ? = d v out v out v in ? ----------------------------- - =
docid023128 rev 5 39/44 A7985A application ideas 44 figure 36. inverting buck-boost regulator the gnd pin of the device is connected to the output voltage so, given the output voltage, the input voltage range is limited by the maximum voltage the device can withstand across vcc and gnd (38 v). therefore, if the output is -5 v, the input voltage can range from 4.5 v to 33 v. as in the positive buck-bo ost, the maximum output current according to application conditions is shown in figure 37 . the dashed line considers a more accurate estimation of the duty cycles given by equation 47 , where power losses across diodes and the internal power mosfet are taken into account. equation 47 figure 37. maximum output current according to switch max. peak current (2.0 a): v o = -5 v d v out v d ? v ? in v sw v out v d ? + ? ---------------------------------------------------------------- - =
package information A7985A 40/44 docid023128 rev 5 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 38. hsop8 package outline ' pp7\s ( pp7\s $0y
docid023128 rev 5 41/44 A7985A package information 44 table 10. hsop8 package mechanical data symbol dimensions (mm) min. typ. max. a 1.70 a1 0.00 0.150 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e1.27 h 0.25 0.50 l 0.40 1.27 k 0.00 8.00 ccc 0.10
ordering information A7985A 42/44 docid023128 rev 5 9 ordering information table 11. ordering information order code package packaging A7985A hsop8 tube A7985Atr hsop8 tape and reel
docid023128 rev 5 43/44 A7985A revision history 44 10 revision history table 12. document revision history date revision changes 19-apr-2012 1 initial release. 08-oct-2012 2 document status promot ed from preliminary data to production data. in section 5.6 changed temperature value from 130 to 120 c. 04-jul-2013 3 updated values for v fb parameter in table 4: electrical characteristics . 12-aug-2013 4 changed v fb parameter in table 4: electrical characteristics from 0.594 to 0.588. 17-mar-2014 6 updated figure 34: positive buck-boost regulator on page 36 (replaced by a new figure). updated section 8: package information on page 40 (reversed order of figure 38 and ta ble 10 , minor modifications). updated cross-references throughout document. minor modifications throughout document.
A7985A 44/44 docid023128 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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